Knowledge note
Ascend NPU
A hardware topic hub for Ascend NPU architecture, AI Core execution, memory hierarchy, and scale-up interconnects.
Ascend NPU
This topic collects hardware-level readings of Ascend NPUs and the software or kernel concepts needed to understand their execution model.
- Ascend 950 NPU Architecture: Compute, Memory, and Unified Bus — Third-generation DaVinci Cube/Vector compute, HiF8 and MX formats, chiplet UMA memory, NDDMA, STARS2.0, Unified Bus/URMA/CCU, DVPP, and 8,192-card supernodes.
- Triton Ascend Operator Mechanisms: Vector, Cube, and CV Fusion — Practical mapping from Triton tiles to Ascend AI Core buffers, movement engines, instruction queues, Vector/Cube execution, and CV fusion.
- vLLM-Ascend Architecture — Software integration path from vLLM’s model-serving stack to Ascend platforms, attention backends, HCCL, and device execution.